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Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
FEATURES
* 10 differential 2.5V/3.3V LVPECL / ECL outputs * 2 selectable differential input pairs * CLKx, nCLKx pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input * Output skew: 30ps (typical) * Part-to-part skew: 140ps (typical) * Propagation delay: 2ns (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85310I-11 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V ECL/ HiPerClockSTM LVPECL Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLKx, nCLKx pairs can accept most standard differential input levels. The ICS85310I-11 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and partto-part skew characteristics make the ICS85310I-11 ideal for those clock distribution applications demanding well defined performance and repeatability.
,&6
BLOCK DIAGRAM
CLK0 nCLK0 CLK1 nCLK1 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 CLK_SEL Q3 nQ3 D Q LE Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9
PIN ASSIGNMENT
VCCO
32 31 30 29 28 27 26 25 VCC CLK_SEL CLK0 nCLK0 CLK_EN CLK1 nCLK1 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO
VCCO
nQ0
nQ1
nQ2
CLK_EN
ICS85310I-11
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
Q0
Q1
Q2
24 23 22 21 20 19 18 17
Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Type Description
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 9, 16, 25, 32 10, 11 1 2, 13 14, 15 1 7, 18 1 9, 20 21, 22 23, 24 26, 27 2 8, 29 30, 31 Name VCC CLK_SEL CLK0 nCLK0 CLK_EN CLK1 nCLK1 VEE VCCO nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Power Input Input Input Input Input Input Power Power Output Output Output Output Output Output Output Output Output Output Core supply pin. Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, Pulldown selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Negative supply pin. Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 Units pF K K
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Outputs Selected Source CLK0, nCLK0 Q0:Q9 Disabled; LOW Q0:Q9 Disabled; HIGH
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs CLK_EN 0
1 CLK1, nCLK1 Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described in Table 3B.
Disabled
CLK0, nCLK0 CLK1, CLK1
Enabled
CLK_EN
nQ0:nQ9 Q0:Q9
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK0 or CLK1 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK0 or nCLK1 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q9 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:Q9 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VCC Outputs, VCCO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40C TO 85C
Symbol VCC VCCO IEE Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Test Conditions Minimum 2.375 2.375 Typical 3.3 3.3 Maximum 3.8 3.8 120 Units V V mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 2.375V TO 3.8V, TA = -40C to 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL, CLK_EN CLK_SEL, CLK_EN CLK_EN CLK_SEL CLK_EN CLK_SEL Test Conditions Minimum 2 -0.3 VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -150 -5 Typical Maximum VCC + 0.3 0.8 5 150 Units V V A A A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 Test Conditions VCC = VIN = 3.8V VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V VCC = 3.8V, VIN = 0V -5 -150 0.15 1.3 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V.
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 1.0 VCC - 1.7 0.85 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40C TO 85C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 2.375V TO 3.8V, TA = -40C TO 85C
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% 20% to 80% 200 200 500MHz 2 30 140 Test Conditions Minimum Typical Maximum 700 2.5 55 340 700 700 53 Units MHz ns ps ps ps ps %
tPD tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle 47 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCO = 2V
VCC
Qx
SCOPE
nCLK0, nCLK1
LVPECL
nQx CLK0, CLK1
V
PP
Cross Points
V
CMR
V EE
VEE = -0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
80%
80% V
SW I N G
nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ9 Q0:Q9
tPD
20% Clock Outputs t
R
20% t
F
OUTPUT RISE/FALL TIME
nQ0:nQ9 Q0:Q9
Pulse Width t
PERIOD
PROPAGATION DELAY
odc =
t PW t PERIOD
odc & tPERIOD
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K CLK_IN + V_REF
-
C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50 5 2 Zo FOUT Zo = 50 FOUT 50 50 VCC - 2V FIN FIN Zo = 50
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 5 2 Zo
RTT =
1 (VOH + VOL / VCC -2) -2
Zo
FIGURE 3A. LVPECL OUTPUT TERMINATION
85310AYI-11
RTT
Zo = 50 3 2 Zo 3 2 Zo
FIGURE 3B. LVPECL OUTPUT TERMINATION
REV. D OCTOBER 23, 2002
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Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85310I-11. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85310I-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 120mA = 456mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30.2mW = 302mW
Total Power_MAX (3.8V, with all outputs switching) = 456mW + 302mW = 758mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.758W * 42.1C/W = 117C. This is below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE qJA
FOR
32-PIN LQFP, FORCED CONVECTION
q by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 4.
VCCO
Q1
VOUT RL 50 VCCO - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H = [(V
OH_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
q by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85310I-11 is: 1034
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
Marking ICS85310AYI11 ICS85310AYI11 Package 32 lead LQFP 32 lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85310AYI-11 ICS85310AYI-11T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85310AYI-11
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REV. D OCTOBER 23, 2002
Integrated Circuit Systems, Inc.
ICS85310I-11
LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change AC Characterisitics table - tPD row, revised value from 2.25ns Max. to 2.5ns Max. Added Termination for LVPECL Outputs section. Added LVPECL DC Characterisitics table. Changed par t number from ICS85310-11 to ICS85310I-11 in title and all subsequent areas throughout the datasheet. Power Supply table - increased max. value for IEE to 120mA from 30mA max. Power Considerations have re-adjusted to the increased IEE value. Date 4/29/02 5/29/02 7/25/02 10/23/02
Rev B
Table T5
Page 5 9 5
4D C D T4A
4 10
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